1. Technical Field
The present invention relates to an analog signal level detecting apparatus for detecting a level of an analog signal, such as an audio signal typically.
2. Prior Art
FIG. 4 shows an analog signal level detecting apparatus in a prior art. In FIG. 4, reference numeral 1 shows an input terminal, to which an analog signal is provided. Reference numeral 2 shows a reference bias voltage input terminal, to which a reference bias voltage is provided. Reference numeral 3 shows a full-wave rectifying circuit, which compares the provided analog signal with the provided reference bias voltage and reverses a negative area so as to be positive. Reference numeral 4 shows a capacitor for smoothing, which integrates the rectified voltage obtained by the full-wave rectifying circuit 3 and coverts it into a direct-current (DC) voltage. Reference numeral 5 shows an output terminal of the analog signal level detecting apparatus.
It is an object of the analog signal level detecting apparatus to properly convert the rectified analog signal into a DC voltage by integrating with the capacitor. For that purpose, a time constant determined by the capacitance of the capacitor 2 should be large for the maximum signal cycle of the provided analog signal. As a result, the capacitor 4 has an extremely too large capacitance to be integrated on an integrated circuit.
In order to solve the problem, Japanese Patent No. 2790176 already proposed an analog signal level detecting apparatus, which does not require such a capacitor with a large capacitance incapable of being integrated on an integrated circuit.
FIG. 5 is a block diagram showing a basic circuit configuration of the analog signal level detecting apparatus disclosed in the Japanese Patent No. 2790176. FIG. 6 is a timing wave chart useful for understanding the operation of the analog signal level detecting apparatus shown in FIG. 5. In FIG. 5, reference numeral 6 shows a full-wave rectifier performing full-wave rectification of an analog signal V1. Reference numeral 7 shows a comparator. Reference numeral 9 shows an up/down counter selectively performing an up-count operation and a down-count operation according to a level of an output signal of the comparator 7. Reference numeral 8 shows a digital-analog converter converting the count value of the up/down counter 9 into a DC voltage.
The analog input signal V1 is provided to an input terminal A of the full-wave rectifier 6 and is rectified by the full-wave rectifier 6. An output signal V2, which appears in an output terminal B of the full-wave rectifier 6, becomes a full-wave rectified shape. FIG. 6(a) shows the analog input signal V1 with a sinusoidal wave as one example. Its period is 1/F where F is frequency. In addition, FIG. 6(b) shows the output signal V2 of the full-wave rectifier 6.
The output terminal B of the full-wave rectifier 6 is connected to one input terminal of the comparator 7. Another input terminal of the comparator 7 is connected to an output terminal C of the digital-analog converter 8.
The input terminal of the digital-analog converter 8 is connected to the output terminal of the up/down counter 9. The frequency f of the up-count operation and the down-count operation of this up/down counter 9 is determined by the frequency of the clock signal D provided to the up/down counter 9. An output signal V3 of the digital-analog converter 8 takes a value corresponding to a change of the count value of the up/down counter 9, and is provided to another input terminal of the comparator 7. FIG. 6(b) shows the output signal V3 of the digital-analog converter 8 with overlapping on the output signal V2 of the full-wave rectifier 6.
As seen in FIG. 6, the output signal V3 of the digital-analog converter 8 increases when the up/down counter 9 performs up-count, and decreases when down-count.
In addition, when the output signal V2 of the full-wave rectifier 6 is larger than the output signal V3 of the digital-analog converter 8, the level of the output signal V3 of the digital-analog converter 8 increases at a constant slope. On the other hand, when the output signal V2 of the full-wave rectifier 6 is smaller than the output signal V3 of the digital-analog converter 8, the level of the output signal V3 of the digital-analog converter 8 decreases at a constant slope.
In this case, the output signal V3 of the digital-analog converter 8 increases or decreases at a period 1/f in stages at the same amount every stage. Thus, the slope in increasing is the same as the slope in decreasing.
An average value Vm of the output signal V3 of the digital-analog converter 8 represents an effective value of the input signal.
However, in the analog signal level detecting apparatus disclosed in the Japanese Patent No. 2790176, both the operation frequencies in the up-count operation and the down-count operation of the up/down counter are uniquely determined by the frequency of the common clock signal D. Accordingly, the time inclination when the count value increases is the same as the time inclination when the count value decreases.
Therefore, in the prior art, since the output responsivity for the level change of the analog signal V1 cannot be arbitrarily selected, the output signal V3 of the digital-analog converter 9 representing the effective value of the analog signal V1 varies in stages as a triangle wave.
For example, when the analog signal level detecting apparatus disclosed in the Japanese Patent No. 2790176 is used as means for obtaining a control signal of an audio AGC circuit, which controls a gain according to a level of an analog audio signal, the following situation happens. That is, although the effective value level of the analog input signal V1 is constant, the level of output signal V3 of the digital-analog converter 9 representing the effective value varies as a triangular wave. Accordingly, since the gain of the audio AGC circuit varies according to the change of the triangle wave, the level of the output audio signal of the AGC circuit constantly repeats extension and compression. Therefore, the audio signal causes a feeling that something is wrong.
In addition the digital-analog converter as a preferred embodiment proposed in the above Japanese Patent No. 2790176 is controlled by a switching control signal, which is generated according to the count number of the up/down counter, as a capacitor switching method.